Wiki code for Flag Day and Heads Up: Power Aware Dispatcher and Deep C-States

Hide Line numbers
1: == Flag Day and Heads Up: Power Aware Dispatcher and Deep C-States
2: 
3: {{{
4: 
5: Date: Wed, 25 Feb 2009 21:31:24 -0800
6: From: Eric Saxe <Eric.Saxe at sun dot com>
7: To: on-all at sun dot com, onnv-gate at onnv dot eng dot sun dot com
8: Subject: Flag Day and Heads Up: Power Aware Dispatcher and Deep C-States
9: 
10: Greetings,
11: 
12: Our putback of:
13: PSARC 2008/777 cpupm keyword mode extensions
14: PSARC 2008/663 cpu deep idle keyword
15: 6567156 bring CPU power awareness to the dispatcher
16: 6700904 deeper C-State support required on follow-ons to Intel Penryn
17: processor generation microarchitecture
18: 6805661 cmt_root may contain duplicates on UMA systems
19: 
20: ...introduces into OpenSolaris the Power Aware Dispatcher project, which
21: includes support for Intel’s Deep Power Down (a.k.a Deep C-states) power
22: management feature beginning with the Core i7 (Nehalem) processor
23: microarchitecture.
24: 
25: This integration also represents a flag-day for Install(1) users, as the
26: kernel, the pmconfig(1M) and powertop(1M) commands are all touched, and
27: should be upgraded (or downgraded) together. Failure to heed this flag
28: day may result in an assert being tripped (in the case of a mismatched
29: pmconfig(1M)). BFU will do do the right thing.
30: 
31: The Power Aware Dispatcher project extends the kernel’s CMT scheduling
32: infrastructure with awareness of CPU power management domains (groups of
33: logical CPUs that may be power managed), which it uses to implement
34: thread placement strategies that deliver superior performance, while
35: facilitating (and driving) power management of underutilized CPU resources.
36: 
37: In the "tickless" spirit, PAD also introduces an event-based CPU power
38: management implementation, where CPU power state changes are driven by
39: utilization "events" delivered by the dispatcher that are triggered by
40: changes in power domain utilization.
41: 
42: Event based CPUPM is enabled by default, however polling based CPUPM may
43: still be used by explicitly specifying it via the optional cpupm keyword
44: "mode" argument in power.conf(4).
45: 
46:    cpupm enable poll-mode
47: 
48: Please note that support for Deep C-states is initially available only
49: on Intel’s Nehalem based processors, which implement a Time Stamp
50: Counter (TSC) register (used by OpenSolaris as the high resolution time
51: source) that remains invariant across deep C-state transitions.
52: 
53: Some Nehalem based systems may use BIOSes that do not enable Deep
54: C-states by default. On such systems, you may need to ensure that the
55: ACPI C2 and C3 states are enabled before OpenSolaris can make use of
56: them. These states may also appear in BIOS as Intel defined C-states C3
57: through C7. In some cases, a BIOS upgrade may be required to utilize
58: Deep C-states.
59: 
60: Deep C-States can be disabled in BIOS, and may also be disabled by
61: including the following line in /etc/system:
62:    set idle_cpu_no_deep_c = 1;
63: 
64: They may also be enabled/disabled via the cpu_deep_idle power.conf(4)
65: keyword:
66:    cpu_deep_idle    disable
67: or
68:    cpu_deep_idle    enable
69: 
70: Bugs may be reported under bugster via solaris/kernel/sched, and may
71: also be reported to tesla-dev at opensolaris dot org
72: 
73: On behalf of the PAD team:
74:    Bill Holler <bill.holler at sun dot com>
75:    Mark Haywood <mark.haywood at sun dot com>
76:    Anup Pemmaiah <napanda.pemmaiah at sun dot com>
77:    Aubrey Li <aubrey.li at intel dot com>
78:    Pat Bredenberg <patrick.bredenberg at sun dot com>
79:    Darrin Johnson <darrin.johnson at sun dot com>
80:    ...and myself,
81: 
82: Thanks and enjoy.
83: -Eric
84: 
85: }}}
OpenSolaris

Top Menu

Wiki code for Flag Day and Heads Up: Power Aware Dispatcher and Deep C-States

Search

Collectives

Community Group

Project

User Group

Subsites

Community Group on Pages
